A serial communication protocol designed for short-distance communication between integrated circuits on the same circuit board.
Uses one or more Master-devices that distribute work to the slave-devices.
Key Features
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Data frame size is 8 bits.
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Two-wire interface: Uses just two bidirectional lines - Serial Data Line (SDA) and Serial Clock Line (SCL)
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Master-slave architecture: One or more master devices control the communication with multiple slave devices
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Address-based: Each slave device has a unique address, allowing up to 128 devices on a single bus (more with extended addressing)
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Synchronous communication: The clock signal coordinates data transfer
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Multi-master capability: Multiple devices can act as masters on the same bus
- Can result in issues if two master tries to transmit at the same time, which must be mitigated by checking if SDA line is high before sending.
Examples
One Master Multiple slaves
